1. Field of the Invention
The present invention relates to multilayer capacitor greatly reducing the equivalent serial inductance (ESL) and production method thereof, more particularly relates to a multilayer capacitor used as a decoupling capacitor etc.
2. Description of the Related Art
In recent years, while advances have been made in reducing the voltage of power sources used for supplying power to large-scale integrated circuits (LSI's) and other integrated circuits, the load current has increased.
Therefore, it has become extremely difficult to keep fluctuations in the power source voltage to within tolerances when faced with rapid changes in the load current. Therefore, as indicated in FIG. 2, a decoupling capacitor 100 (for example two-terminal structure multilayer ceramic capacitor) is now being connected to a power source 102. At the time of transitory fluctuation in the load current, current is supplied from this multilayer ceramic capacitor 100 to the LSI 104 of the central processing unit (CPU) etc. to suppress fluctuation of the power source voltage.
Along with the increasingly higher operating frequencies of today's CPU's, however, the fluctuations in the load current have become faster and larger. Multilayer ceramic capacitor 100 having the equivalent serial inductance (ESL), shown in FIG. 2, itself now has a great impact on fluctuations of the power source voltage.
That is, since the ESL is high in a conventional multilayer ceramic capacitor 100, fluctuation of the power source voltage V easily becomes greater in the same way as above along with fluctuations in the load current i.
That is because the fluctuations in voltage at the time of transition of the load current are approximated by the following equation 1 and therefore the level of the ESL is related to the magnitude of fluctuation of the power source voltage. Further, from equation 1, reduction in the ESL can be said to be linked with stabilization of the power source voltage.dV=ESL·di/dt  equation 1where,
dV is transitory fluctuation of voltage (V),
di is the fluctuation of current (A), and
dt is the time of fluctuation (sec).
As a multilayer capacitor wherein the ESL is reduced, a multilayer capacitor shown in Japanese Patent Application Laid Open No. 2004-140183 is known. In the multilayer capacitor shown in the Japanese Patent Application Laid Open No. 2004-140183, conductor layers are positioned perpendicularly to a ground plane (in a capacitor, a side face opposed to a substrate). According to the multilayer capacitor, the ESL can be reduced less than 250 pH. Along with the increasingly higher operating frequencies of CPU's, however, further reducing the ESL is required. Also, recently, due to an operating voltage of IC has become as low as a level of 1V, under a condition that current fluctuation level di/dt is 1000 A/μsec, an ultra voltage dV must be set within a range of ±60 mV (an acceptable range within ±6% of 1V of the operating voltage of IC). Therefore, the ESL is required to be reduced less than 60 pH (∴from equation 1, ESL=dv/(di/dt)=60×10−3/1000/10−6=60 pH).
Further, as a multilayer capacitor wherein the ESL is reduced, a multi-terminal multilayer capacitor is known. In the multi-terminal multilayer capacitor, by increasing external terminal electrode, current flow varying in direction can be realized in a conductor layer. As a result, further reducing of the ESL becomes possible.
However, in the multi-terminal capacitor, there are problems that preparing a plurality of conductor layer patterns is necessary, and that increasing number of external terminals results in higher manufacturing cost.